Google Hardware Engineering Internship

 

Google Hardware Engineering Internship

Minimum qualifications:

Currently enrolled in an Associate, Bachelor's, or Master's degree program, post-secondary, or training experience in Electrical Engineering.

Experience in Hardware or Electrical Engineering.

Experience with design concepts and computer hardware architecture.

Preferred qualifications:

Experience in one or more of the following areas: SoC/ASIC Design, Design Verification, Physical Design, Design for Testability.

Experience with Verilog/HDL or System Verilog coding.

Experience with one of the scripting languages (e.g., PERL, TCL, Python, etc.).

Experience with EDA tools and methodologies like Lint, CDC, Synthesis, Formal Equivalence or low Power reduction techniques.

Available to work full-time for a minimum of 6 months outside of university term time.

About the job

Our Winter internships will start in January 2023 and will be 22-24 weeks in duration.

As a Hardware Engineering intern, you will design, develop, and deploy next-generation consumer hardware. Google's Consumer Hardware Silicon division (gChips) builds chips (SoCs and ASICs) optimized for Google-branded consumer devices.

As a member of this team, you will use a range of engineering experience to explore solutions to a variety of engineering problems. Additionally, as an Electrical Engineer, you will participate in the design, analysis, and prototyping of concepts.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Hardware team researches, designs, and develops new technologies and hardware to make our user's interaction with computing faster, more powerful, and seamless. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, our Hardware team is making people's lives better through technology.

Responsibilities

Work with the team to develop power and performance-optimized chips.

Contribute to the design, verification, and silicon implementation of chips.

Collaborate with local and remote teams in automating design flows.

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